FIG. 1 shows a conventional P-channel insulated gate field effect transistor (P-IGFET), e.g., a P-channel metal oxide semiconductor field effect transistor (P-MOSFET), stacked gate NVM cell 100 formed in an N-type region 102 of semiconductor material (e.g., a crystalline silicon substrate). The N-type region 102 is typically an N-well formed in a P-type silicon substrate. The NVM cell 100 typically includes a polysilicon floating gate 104 that is separated from the N-type region 102 by a layer of thin “gate” silicon dioxide 106. A polysilicon control gate 108 is separated from the floating gate 104 by a layer of dielectric material 110, typically a sandwich of oxide-nitride-oxide (ONO). Two P-type diffusion regions 112 are formed in the N-type region 102 at the sides of the stacked gate structure to provide the source and drain regions of the NVM cell 100, defining an N-type channel region 114 between them. Integrated circuit fabrication techniques for making the NVM cell 100 are well known in the industry.
As is also well known, the conventional programming method for the NVM cell 100 uses hot electron injection. When applied to a stacked gate NVM cell 100, the hot electron injection programming method assumes that a high negative voltage is applied to the drain region of the cell 100. Depending upon the erasing and coupling coefficient(s), a corresponding voltage is applied to the control gate 108, thereby bringing the potential of the floating gate 104 to a value that is negative, but lower in absolute value as compared with the drain potential. Under these bias conditions, a high lateral electrical field is generated, thereby creating hot electrons that are affected by a high perpendicular electrical field such that the hot electrons tunnel through the thin gate oxide 106 to reach the floating gate 104. The amount of injection current depends primarily upon the potentials of the drain region and floating gate electrode 104 such that, with more drain voltage, more injection takes place. Further discussion of the NVM cell 100 and its programming technique will be found in U.S. Pat. No. 6,137,723, issued Oct. 24, 2000, which is incorporated herein by reference in its entirety to provide background information regarding the present invention.
FIG. 2 shows the NVM memory cell 100 of FIG. 1 in electrical schematic form, including a body-connected N-type source region 112s and an N-type drain region 112d. 
Referring to FIG. 3, co-pending and commonly-assigned U.S. patent application Ser. No. 10/895,710, titled “Improved Nonvolatile Memory Cell”, filed by Poplevine et al. on Jul. 8, 2004 (now U.S. Pat. No. 6,992,927), discloses an NVM memory cell 200 that includes four P-IGFETs connected to a common storage node Ns, with one P-IGFET transistor for each of the four primary cell functions: program (or write), read, erase and control. U.S. Pat. No. 6,992,927 is hereby incorporated by reference in its entirety.) The NVM cell 200, while being somewhat larger in size or circuit area than the conventional stacked gate cell 100 described above, allows for independent and improved optimization of each cell function.
The programming function of the 4-transistor NVM cell 200 is controlled by a first PMOS programming transistor Pw with interconnected source and bulk regions to which a programming voltage Vp is applied. A programming signal Dp is applied to the drain of transistor Pw. The gate electrode of programming transistor Pw is connected to the common storage node Ns.
The read function of the NVM cell 200 is controlled by a second PMOS read transistor Pr having interconnected source and bulk regions to which a read voltage Vr is applied, a drain region from which a read signal Dr is received, and a gate electrode connected to the common storage node Ns.
The erase function of the NVM cell 200 is controlled by a third PMOS erase transistor Pe having interconnected drain, source and bulk regions to which an erase voltage Ve is applied, and a gate electrode connected to the common storage node Ns.
The control function of the NVM cell 200 is controlled by a fourth PMOS control transistor Pc having interconnected drain, source and bulk regions to which a control voltage Ve is applied, and a gate electrode connected to the common storage node Ns.
The NVM cell 200 can be programmed in any of a number of ways, including conventional techniques as follows. During programming, or writing, the programming voltage Vp (e.g., approximately 5 volts) is applied to programming transistor Pw as described above, with all other electrodes being connected to the circuit reference potential (e.g., ground). During erasing, an erase voltage Ve (e.g., approximately 10 volts) is applied to the erase transistor Pe, with all other electrodes connected to the circuit reference potential. During reading, a read voltage Vr (e.g., approximately 1 volt) is applied to read transistor Pr, and all other electrodes are connected to the circuit reference potential. (Such voltages are typical for oxide thicknesses in the range of 60–80 Angstroms.)
FIG. 4 shows the 4-transistor NVM cell 200 of FIG. 3 adapted to include additional PMOS transistor P1 and NMOS transistors N1, N2 for facilitating the use of the NVM cell 200 within an NVM cell array. For example, to read data from the common storage node Ns, P-channel pass transistor P1 is used. To program data to the common storage node Ns, a cascade circuit that includes the two N-channel pass transistors N1, N2 is used to prevent a high voltage from appearing between a gate electrode and a drain or source region.
FIG. 5 shows a plurality of NVM memory cells 200, adapted as shown in FIG. 4, incorporated into an NVM cell array 300. The NVM cell array 300 includes M columns of adapted cells 200 and N rows of adapted cells 200. The program word line PWL is utilized to select the rows of the array 300 to be programmed, while the read word line RWL is utilized to select the rows of the array to be read. The erase voltage Ve, the program voltage Vp, the control voltage Vc and the read voltage Vr are applied to each cell directly. With no high voltage switches or other supporting circuitry, significantly simplified connections can be made from the array 300 to external or internal voltage and signal sources and to the signal destinations.
The operational modes of erase, program and read for the array 300 are similar to those described above for a single NVM cell 200. During the erase mode, the program word lines PWL(0)–PWL(N-1) are at a logic low, the read word lines RWL(0)–RWL(N-1) are at a logic high, the erase voltage Ve is applied, and the rest of the signal lines are at circuit reference potential. This causes all cells in the array 300 to be erased.
During the programming mode, the read word lines RWL(0)–RWL(N-1) are at a logic high, one of the program word lines, e.g., PWL(0), is at a logic high while the remaining program word lines, e.g., PWL(1)–PWL(N-1), are at a logic low. To program a particular cell 200 in the array 300, the corresponding program bit line, e.g., PBL(0), is at a logic low. To erase the remaining cells in the array 300, the corresponding program bit lines, e.g., PBL(1)–PBL(M-1), are left floating. The program voltage Vp is applied to all cells in the array 300, while the remaining electrodes are at circuit reference potential.
During the read mode, the program word lines PWL(0)–PWL(N-1) are at a logic low, one of the read word lines, e.g., RWL(0), is at a logic low, while the remaining read word lines, e.g., RWL(1)–RWL(N-1) are at a logic high. On each of the read bit lines RBL(0)–RBL(M-1), a high current or voltage is received for each corresponding cell in the array 300 that had been programmed, while a low current or voltage is received for each corresponding cell that had been erased. The read voltage Vr is applied to all cells in the array 300, while the remaining electrodes are at circuit reference potential.
Different mechanisms and different program modes for the NVM cell 200 and for the array 300 are described in the following three co-pending and commonly-assigned U.S. patent applications: application Ser. No. 10/895,711, titled “Programming Method for Nonvolatile Memory Cell”, filed by Poplevine et al. on Jul. 8, 2004 (now U.S. Pat. No. 7,042,763); application Ser. No. 10/895,713, titled “Programming Method for Nonvolatile Memory Cell”, filed by Poplevine et al. on Jul. 8, 2004 (now U.S. Pat. No. 6,985,386); and application Ser. No. 10/895,712, titled “Programming method for Nonvolatile Memory Cell”, filed by Poplevine et al. on Jul. 8, 2004 (now U.S. Pat. No. 7,020,027). (Each of these three patents is hereby incorporated by reference in its entirety.)
Co-pending and commonly-assigned U.S. patent application Ser. No. 11/182,115 titled “Reverse Fowler-Nordheim Tunneling Programming For Non-Volatile Memory Cell”, filed by Poplevine et al. on the same date as this patent application, discloses an alternate method for programming the FIG. 4 NVM cell. application Ser. No. 11/182,115 is hereby incorporated by reference in its entirety.
More specifically, application Ser. No. 11/182,115 discloses a programming method that utilizes reverse Fowler-Nordheim (FN) tunneling to program the above-described 4-transistor NVM cell 200. When the potential difference between floating gate and drain and source and body exceeds the tunneling threshold voltage (VFN), electrons tunnel from drain and source to the gate. This makes the floating gate negatively charged.
The programming conditions for the NVM cell 200 in accordance with the disclosure of application Ser. No. 11/182,115 are shown in FIG. 6. The read voltage Vr, the read signal Dr and the erase voltage Ve are connected to an inhibiting voltage VN. Inhibiting voltage VN should be at a level high enough that prevents reverse Fowler-Nordheim tunneling, but low enough to ensure no forward tunneling. The inhibiting voltage VN depends on gate oxide thickness; for example, VN˜3.3V for a gate oxide thickness of 70 Å. Setting the read voltage Vr, the read signal Dr and the erase voltage Ve to VN is done to prevent the read transistor Pr and the erase transistor Pe from being programmed. The programming voltage Vp and programming signal Dp of the program transistor Pw are both tied to 0V. The voltage Vnw can be tied to either 0v or to Vdd. The control gate voltage Vc is then swept from 0V to a predefined maximum voltage Vcmax in a preselected programming time Tprog. The programming time Tprog is in the range of tens of milliseconds. The programming time Tprog affects the amount of negative charge that will tunnel to the floating gate (FG in FIG. 6).
The maximum voltage Vcmax must exceed the tunneling threshold voltage VFN; it affects the amount of negative charge to put on the floating gate. The voltage applied to Vc is coupled through control transistor Pc to the floating gate FG. When voltage at the floating gate FG reaches the tunneling threshold voltage VFN, then electrons tunnel from the drain/source/body of the program transistor Pw to the floating gate FG, making the floating gate FG more negative. The tunneling process continues as control gate voltage Vc is swept. At the end of the program cycle, the control gate voltage Vc is ramped back down to 0v. As a result of this process, the floating gate FG is left with a net negative charge from the reversed Fowler-Nordheim tunneling program.
There is no current consumption in the read transistor Pr, the erase transistor Pe or the control transistor Pc during the programming process. The only current is the Fowler-Nordheim tunneling current, which is about 10 pA per transistor. Those skilled in the art will appreciate that this allows the use of a smaller charge pump.
NVM cells not selected to be programmed are inhibited from being program. This is done by applying the inhibiting voltage VN to all of the electrodes (Vr, Dr, Ve, Dp, Vp and Vnw) of the unselected cells.